1) Field of the Invention
This invention relates to the design and manufacture of integrated circuits and more particularly to a method of estimating properties of an integrated circuit.
2) Description of the Background Art
In the design and manufacture of integrated circuits it is required to estimate particular properties of an integrated circuit. An example of such a property is the sensitivity or susceptibility to extra material defects. Extra material critical area is a measure of an integrated circuit layout geometry that defines the susceptibility of the device to extra material defects of a given size. Such defects are small randomly occurring particles of foreign matter, of varying size, present in the manufacturing process. These defects can fatally damage an integrated circuit during manufacture. It is common practice to extract and compute a value for extra material critical area for a range of discrete defect sizes. These results are combined to give an estimate of the susceptibility to extra material defects as a whole. Those skilled in the art can combine knowledge of the defects within the manufacturing process with the susceptibility to these defects to estimate the associated yield loss. A similar treatment can be applied to other defect types, such as missing material, pinhole, inter-level dielectric defects and defective contacts and vias. The susceptibility of the integrated circuit to a range of defect types and the levels of these defects within the manufacturing process can be used by those skilled in the art to estimate the manufacturing yield of the device. This can in turn be used to estimate the cost of production and also the number of devices that must be manufactured in order to produce the required number of working devices.
The determination of the susceptibility of an integrated circuit to defects is commonly obtained by a computer analysis of the integrated circuit mask layout. It is not uncommon for such an analysis to require hundreds of hours of computer time and a large amount of computer memory. A substantial cost must be incurred to estimate these properties and other properties of an integrated circuit.
Techniques have been developed to speed up the required computer analysis by the use of a network of computers which execute the task as sub tasks in parallel. This has the obvious disadvantage that a network of computers must be provided at high cost. There is also the additional burden of managing the distribution of the calculation over the network, which is typically in use by other users for different applications.
Another method commonly used to reduce the time to extract properties is to exploit the hierarchy of the integrated circuit design. In its simplest form the interactions between cells, i.e., discrete areas of the design, are ignored. The technique consists of an analysis of each cell within a design to estimate the property of the cell. This property is then multiplied by the number of copies of the cell within the design. The technique is limited by the nature of the design hierarchy. Integrated circuits that are largely made up of multiple copies of a single or a few cells can be analysed quickly. However, many integrated circuit devices do not follow this pattern. Designs may be composed of a single large cell, or a collection of cells routed together within a single large cell. Other designs are composed of a large number of different cells that may only have a single or few copies within the design. This is particularly true of the more complex high value parts, where each cell is tuned to optimize performance. Consequently, the speed up may not be large.
The simplest form of hierarchical extraction ignores interactions between cells. This almost always leads to a degree of inaccuracy. The level of inaccuracy is not easily predicted, and can be large. Consequently, it is not possible to use the results with confidence. In more complex embodiments interactions between cells are included. This ensures that the results are accurate, but at a cost. The implementation is considerably more difficult. The analysis takes longer since the interaction region, which can be large, must also be processed. It is even possible for the results of a hierarchical analysis, including interactions, to take longer to process than a flat representation. This can occur where the total of the cells plus their surrounding interaction region are greater than a flat representation. This situation is becoming even more likely with the increase in routing levels and the use of automated routing over cells at different levels in the hierarchy.
Even exploiting the hierarchy of a design the extraction of device properties can still take a considerable time. The hierarchical technique has been combined with parallel extraction. This is an obvious extension since that extraction is naturally broken into a number of separate tasks, the extraction from individual cells and their interaction region. These tasks can be accomplished in parallel using a network of computers. This is a costly solution in that it combines a complex implementation with costly hardware. Both the complex software and its use within a network, which can be subject to change, must be maintained at substantial cost.
Another technique used to extract properties of an integrated circuit layout is for a person skilled in the art to analyse the representation and select a region that is characteristic of the device as a whole, or some significant part of the device. This kind of solution can be used where a design, or a block within the design, largely consists of similar cells. For example standard family cells may be connected by routing. A region that appears characteristic of the whole is selected. An analysis of this region is used to approximate the whole design or block. The technique is effectively an extension of the hierarchical extraction technique, in that it attempts to chose a representative region that is assumed to have a number of similar occurrences throughout a device or a specified part of the device.
The disadvantage of this approach is that it requires a person skilled in the art to select an appropriate characteristic block or blocks. A further disadvantage is that results based on this approach can be very variable depending on the skill of the practitioner, the actual layout and characteristic region selected. It is also difficult to determine how much reliance can be placed on any estimate. Also, not all integrated circuit designs are suitable for this method since they may be highly variable and not contain blocks that obviously contain similar cells or characteristics.
The technique of characterising layout has been extended to the characterisation of particular design environments used for automated integrated circuit design, in particular, to compare the manufacturability and other characteristics of different design environments. This is achieved by extracting the characteristics of a range of variably sized partitions of one or more integrated circuit layouts that have been generated by the design environment. An obvious extension of this is to use the results to estimate properties of a design based solely on the area of the design. This can be an efficient method of estimating device properties. However, it has a number of limitations. The most obvious limitation is that a design must be composed using a known and characterized design environment. Not all design environments will be simple to characterize, particularly where they are not limited to special applications. Sections of a design created with different design environments must be treated separately and the results combined. Where a design contains parts that are not from a characterized environment, an estimate of properties must be generated by other means. Many designs are composed of parts of existing designs which may have been produce in different design environments and merged. The history of the various parts is not always available and so cannot be used to estimate device properties. In general the technique is only of use where a standard design method is used and a similar class of integrated circuit are designed.